HART-IP Stack

Overview

HART‑IP is the IP‑based transport of the HART protocol, letting any HART master or host system communicate with field devices over standard Ethernet networks instead of the 4–20 mA loop. SES HART-IP stack allows one to connect a HART based sensor directly to Ethernet based network such as APL or enables implementation of a HART Gateway to act as a intermediary between a 4-20 ma device and a Ethernet based IP connected network.

Features of the SES HART-IP stack are:

• Implemented for small, embedded microcontrollers with smaller code and data memory requirements.
• Implements all HART universal commands and many common practice commands
• Implements HART-IP communication security TLS/DTLS per HART-IP specifications 2.0.
• Syslog and Audit Logs features are implemented.
• MDNS to enable device Discovery and Configurations.
• HART Master stack included for discovering attached 4-20 ma devices.
• Web UI Interface for end user configuration and troubleshooting.
• Implemented for STM32, but portable to other platforms.
• SES custom firmware engineering allows for quick migration to your architecture.