SES HART Master Stack

Overview

HART Master stack communicates with a HART enabled 4-20 ma device and collects various device information such as process values, device TAGs, device status, sensor status etc. SES stack has an extensive device information model allowing one to collect most all relevant information which are needed for PLCs or Data Registrars upstream. Thus, the SES Master stack is very useful for HART multiplexors or HART Gateways.

Features of the SES HART Master Stack are:

• Implemented on embedded ARM microcontrollers such as STM32 with smaller code and data memory requirements.
• Implements all HART universal commands and many common practice commands.
• All Data Link Layer timings are properly addressed.
• Burst Mode timings supported.
• Implementation allows for multiple HART channels to be simultaneously supported.
• Extensive device information model for easy handling of data.
• SES custom firmware engineering allows for quick migration to your architecture
• RTOS or Bare Metal implementation is possible.

Contact

Baldev Krishan, Ph.D.
Email: [email protected]
Phone: 510-304-6830
Web: www.smartembeddedsystems.com